1. Field of the Invention
The present invention relates generally to an analog to digital converter, and more particularly to a single slope analog to digital converter for an image sensor.
2. Description of the Related Art
In general, a charge coupled device (CCD) and a CMOS image sensor (CIS) are widely in use as image pickup devices for converting an optical image into an electrical signal.
Manufacturing a CMOS image sensor through a general CMOS process is considered more economical than manufacturing an image pickup device using a CCD, as a CMOS image sensor as an analog to digital converting device can be integrated in a single chip. In addition, a CMOS image sensor is more suitable for low voltage and low power consumption design needed in various mobile applications such as the mobile phones, digital cameras, etc.
A CMOS image sensor may require a high resolution analog to digital converting device for converting an analog signal outputted from an active pixel sensor (APS), reactive to light, into a digital signal.
Analog to digital conversion in a CMOS image sensor may be performed on a chip unit, a column unit, or a pixel unit. A column type analog to digital converter, in which analog to digital conversion is performed on a column unit, is widely in use for commercial purposes due to many advantages related to frame speed, resolution, power consumption, and extensibility.
FIG. 1 shows a single slope analog to digital converter (ADC) 10 according to the related art, and FIG. 2 is a graph related to the operation of the single slope ADC 10 shown in FIG. 1.
Referring to FIGS. 1 and 2, the single slope ADC 10 may include a ramp signal generating unit 11, a comparator 13, a pulse generating unit 15, a counter 17 and a register 19.
The comparator 13 compares a pixel signal Vsig from a pixel in a pixel array with a ramp signal Vramp from the ramp signal generating unit 11 and outputs a comparison result signal Comp. The ramp signal Vramp may decrease or increase with a preset slope.
The pulse generating unit 15 generates a very short pulse signal Pulse_out based on the comparison result signal Comp outputted from the comparator 13 and supply the pulse signal Pulse_out to the register 19.
The counter 17 begins counting according to a preset frequency of a clock signal CLK simultaneously while the comparator 13 is performing the comparing operation, and the count value of the counter 17 is supplied to the register 19.
The register 19 latches and stores the count value received from the counter 17 at the time the pulse signal Pulse_out is received from the pulse generating unit 15.
The above-mentioned single slope ADC of the related art performs the linear analog to digital conversion regardless of the voltage level of a pixel signal, and as such it is unable to perform a conversion optimized for human visual perceptual characteristics.
That is, even through human eyes are generally sensitive in low luminance conditions and insensitive in high luminance conditions, the single slope ADC according to the related art may perform a linear signal conversion to cause the omission of data in low luminance conditions and the saturation of data in high luminance conditions, such that a dynamic range in an image sensor may be reduced.